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-- and other software and tools, and its AMPP partner logic 
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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "02/21/2016 23:07:33"
                                                            
-- Vhdl Test Bench template for design  :  SEG_CONVERTER
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;                              

ENTITY SEG_CONVERTER_vhd_tst IS
END SEG_CONVERTER_vhd_tst;
ARCHITECTURE SEG_CONVERTER_arch OF SEG_CONVERTER_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL i_sys_rst : STD_LOGIC;
SIGNAL i_time_val : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL o_seg_display_val : STD_LOGIC_VECTOR(6 DOWNTO 0);
COMPONENT SEG_CONVERTER
	PORT (
	i_sys_rst : IN STD_LOGIC;
	i_time_val : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	o_seg_display_val : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;
BEGIN
	i1 : SEG_CONVERTER
	PORT MAP (
-- list connections between master ports and signals
	i_sys_rst => i_sys_rst,
	i_time_val => i_time_val,
	o_seg_display_val => o_seg_display_val
	);
clk: PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
	  
	  if( i_time_val = 9 ) then
		i_time_val <= "0000";       
     else 
		i_time_val <= i_time_val + 1; 
     end if;	
		wait for 1000ns;   
--WAIT;                                                       
END PROCESS ;                                           
tb : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
    
	 i_sys_rst <= '1';
	 wait for 100ns;
	 i_sys_rst <= '0';
	 wait for 10ns;
	 -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS ;                                                   
END SEG_CONVERTER_arch;
